а не вспомните, что горело на дисплее di-20he? C или P ? Если выставить в P (parallel) , то звучит заметно лучше, и разница с Berkeley на уровне “показалось”
FPGA data process mode can select either parallel or series mode .
The USB output IIS data is series transmit mode, every data must need one clock cycle to process or transmit, one frame data ( Include L and R data) must need 64 clock cycle to process or transmit, so the data has effect by the 64 clock cycles.
But the parallel data process and transmit mode only need one clock cycle can finish the one frame data process and transmit, that can avoid the effect of clock stability .
The USB input and the S/Pdif decoder output data has recombine become dual 32bit parallel data once input , and the DSD input has recombine become dual 64bit parallel data once input.
The parallel process and transmit mode can improve the sound quality on the transparency and detail but still analog.
In the parallel process mode, all data processing by 256fs clock frequency, but not the usual mode that different sampling music data with 64-256fs variable clock frequency. The fixed 256fs clock frequency makes the signal has more exact timing in phase, process with same timing to keep the sound flavor is same.